The present invention relates to spin-transfer torque magnetoresistive random access memory (STT-MRAM devices), and more specifically, to stack structures and etch processes in STT-MRAM devices.
STT-MRAM devices have some benefits over semiconductor-based memories, such as dynamic random-access memory (DRAM) and static random-access memory (SRAM). However, in order to compete with DRAM and SRAM, the STT-MRAM devices are integrated into the wiring layers of standard silicon logic and memory chips.
STT-MRAM device is a type of solid state, non-volatile memory that uses tunneling magnetoresistance (TMR or MR) to store information. MRAM includes an electrically connected array of magnetoresistive memory elements, referred to as magnetic tunnel junctions (MTJs). Each MTJ includes a free layer and fixed/reference layer that each includes a magnetic material layer. A non-magnetic insulating tunnel barrier separates the free and fixed/reference layers. The free layer and the reference layer are magnetically de-coupled by the tunnel barrier. The free layer has a variable magnetization direction, and the reference layer has an invariable magnetization direction.
An MTJ stores information by switching the magnetization state of the free layer. When magnetization direction of the free layer is parallel to the magnetization direction of the reference layer, the MTJ is in a low resistance state. Conversely, when the magnetization direction of the free layer is antiparallel to the magnetization direction of the reference layer, the MTJ is in a high resistance state. The difference in resistance of the MTJ may be used to indicate a logical ‘1’ or ‘0’, thereby storing a bit of information. The TMR of an MTJ determines the difference in resistance between the high and low resistance states. A relatively high difference between the high and low resistance states facilitates read operations in the MRAM.